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| INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: * The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications * The IC06 74HC/HCT/HCU/HCMOS Logic Package Information * The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines 74HC/HCT4060 14-stage binary ripple counter with oscillator Product specification File under Integrated Circuits, IC06 December 1990 Philips Semiconductors Product specification 14-stage binary ripple counter with oscillator FEATURES * All active components on chip * RC or crystal oscillator configuration * Output capability: standard (except for RTC and CTC) * ICC category: MSI GENERAL DESCRIPTION The 74HC/HCT4060 are high-speed Si-gate CMOS devices and are pin compatible with "4060" of the "4000B" series. They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT4060 are 14-stage ripple-carry counter/dividers and oscillators with three oscillator QUICK REFERENCE DATA GND = 0 V; Tamb = 25 C; tr = tf = 6 ns 74HC/HCT4060 terminals (RS, RTC and CTC), ten buffered outputs (Q3 to Q9 and Q11 to Q13) and an overriding asynchronous master reset (MR). The oscillator configuration allows design of either RC or crystal oscillator circuits. The oscillator may be replaced by an external clock signal at input RS. In this case keep the other oscillator pins (RTC and CTC) floating. The counter advances on the negative-going transition of RS. A HIGH level on MR resets the counter (Q3 to Q9 and Q11 to Q13 = LOW), independent of other input conditions. In the HCT version, the MR input is TTL compatible, but the RS input has CMOS input switching levels and can be driven by a TTL output by using a pull-up resistor to VCC. TYPICAL SYMBOL PARAMETER tPHL/ tPLH propagation delay RS to Q3 Qn to Qn+1 tPHL fmax CI CPD Notes 1. CPD is used to determine the dynamic power dissipation (PD in W): PD = CPD x VCC2 x fi + (CL x VCC2 x fo) where: fi = input frequency in MHz fo = output frequency in MHz (CL x VCC2 x fo) = sum of outputs CL = output load capacitance in pF VCC = supply voltage in V 2. For HC the condition is VI = GND to VCC For HCT the condition is VI = GND to VCC - 1.5 V 3. For formula on dynamic power dissipation see next pages. ORDERING INFORMATION See "74HC/HCT/HCU/HCMOS Logic Package Information". MR to Qn maximum clock frequency input capacitance power dissipation capacitance per package notes 1, 2 and 3 CONDITIONS HC CL = 15 pF; VCC = 5 V 31 6 17 87 3.5 40 31 6 18 88 3.5 40 ns ns ns MHz pF pF HCT UNIT December 1990 2 Philips Semiconductors Product specification 14-stage binary ripple counter with oscillator PIN DESCRIPTION PIN NO. 1, 2, 3 7, 5, 4, 6, 14, 13, 15 8 9 10 11 12 16 SYMBOL Q11 to Q13 Q3 to Q9 GND CTC RTC RS MR VCC NAME AND FUNCTION counter outputs counter outputs ground (0 V) external capacitor connection external resistor connection clock input/oscillator pin master reset positive supply voltage 74HC/HCT4060 Fig.1 Pin configuration. Fig.2 Logic symbol. Fig.3 IEC logic symbol. December 1990 3 Philips Semiconductors Product specification 14-stage binary ripple counter with oscillator DYNAMIC POWER DISSIPATION FOR 74HC PARAMETER total dynamic power dissipation when using the on-chip oscillator (PD) Note 1. GND = 0 V; Tamb = 25 C DYNAMIC POWER DISSIPATION FOR 74HCT PARAMETER total dynamic power dissipation when using the on-chip oscillator (PD) Notes 1. GND = 0 V; Tamb = 25 C 2. Where: fo = output frequency in MHz fosc = oscillator frequency in MHz (CL x VCC2 x fo) = sum of outputs CL = output load capacitance in pF Ct = timing capacitance in pF VCC = supply voltage in V VCC (V) 4.5 TYPICAL FORMULA FOR PD (W) (note 1) VCC (V) TYPICAL FORMULA FOR PD (W) (note 1) 2.0 4.5 6.0 74HC/HCT4060 CPD x fosc x VCC2 + (CL x VCC2 x fo) + 2Ct x VCC2 x fosc + 60 x VCC CPD x fosc x VCC2 + (CL x VCC2 x fo) + 2Ct x VCC2 x fosc + 1 750 x VCC CPD x fosc x VCC2 + (CL x VCC2 x fo) + 2Ct x VCC2 x fosc + 3 800 x VCC CPD x fosc x VCC2 + (CL x VCC2 x fo) + 2Ct x VCC2 x fosc + 1 750 x VCC Fig.4 Functional diagram. APPLICATIONS * Control counters * Timers * Frequency dividers * Time-delay circuits December 1990 4 Philips Semiconductors Product specification 14-stage binary ripple counter with oscillator 74HC/HCT4060 Fig.5 Logic diagram. Fig.6 Timing diagram. December 1990 5 Philips Semiconductors Product specification 14-stage binary ripple counter with oscillator DC CHARACTERISTICS FOR 74HC Output capability: standard (except for RTC and CTC) ICC category: MSI Voltages are referenced to GND (ground = 0 V) Tamb (C) SYMBOL 74HC PARAMETER min. 74HC/HCT4060 TEST CONDITIONS UNIT V VI CC (V) +25 typ. max. -40 to +85 min. max. -40 to +125 min. max. OTHER VIH HIGH level input voltage MR input LOW level input voltage MR input HIGH level input voltage RS input LOW level input voltage RS input 1.5 3.15 4.2 1.3 2.4 3.1 0.8 0.5 2.1 1.35 2.8 1.8 1.5 3.15 4.2 0.5 1.35 1.8 1.7 3.6 4.8 0.3 0.9 1.2 3.84 5.34 3.84 5.34 0.3 0.9 1.2 1.5 3.15 4.2 0.5 1.35 1.8 1.7 3.6 4.8 0.3 0.9 1.2 3.7 5.2 3.7 5.2 1.9 4.4 5.9 1.9 4.4 5.9 3.7 5.2 1.9 4.4 5.9 3.7 5.2 0.33 0.33 0.1 0.1 0.1 0.4 0.4 0.1 0.1 0.1 V 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 4.5 RS=GND -IO = 2.6 mA -IO = 3.3 mA 6.0 and MR=GND VIL V VIH 1.7 3.6 4.8 V VIL V VOH HIGH level output voltage 3.98 RTC output 5.48 V 3.98 5.48 1.9 4.4 5.9 1.9 4.4 5.9 VOH HIGH level output voltage 3.98 CTC output 5.48 HIGH level output voltage 1.9 except RTC output 4.4 V 4.5 RS=VCC 6.0 and MR=VCC -IO = 0.65 mA -IO = 0.85 mA 2.0 4.5 6.0 2.0 4.5 6.0 1.9 4.4 5.9 1.9 4.4 5.9 3.84 5.34 V 2.0 RS=GND -IO = 20 A -IO = 20 A 4.5 and 6.0 MR=GND -IO = 20 A 2.0 RS=VCC 4.5 and 6.0 MR=VCC 4.5 RS=VIH 6.0 and MR=VIL -IO = 20 A -IO = 20 A -IO = 20 A -IO = 3.2 mA -IO = 4.2 mA -IO = 20 A -IO = 20 A -IO = 20 A -IO = 4.0 mA -IO = 5.2 mA IO = 2.6 mA IO = 3.3 mA V V VOH 5.9 VOH HIGH level output voltage 3.98 except RTC and CTC 5.48 outputs LOW level output voltage RTC output 2.0 4.5 6.0 1.9 4.4 5.9 3.84 5.34 0.26 0.26 V 2.0 VIH 4.5 or 6.0 VIL 4.5 VIH 6.0 or VIL 4.5 RS=VCC 6.0 and MR=GND V VOL 0 0 0 December 1990 0.1 0.1 0.1 6 V 2.0 RS=VCC IO = 20 A IO = 20 A 4.5 and 6.0 MR=GND IO = 20 A Philips Semiconductors Product specification 14-stage binary ripple counter with oscillator 74HC/HCT4060 Tamb (C) SYMBOL 74HC PARAMETER min. TEST CONDITIONS UNIT V VI CC (V) +25 typ. max. -40 to +85 min. max. -40 to +125 min. max. OTHER VOL LOW level output voltage CTC output LOW level output voltage except RTC output LOW level output voltage except RTC and CTC outputs input leakage current 0.26 0.26 0 0 0 0.1 0.1 0.1 0.26 0.26 0.1 0.33 0.33 0.1 0.1 0.1 0.33 0.33 1.0 0.4 0.4 0.1 0.1 0.1 0.4 0.4 1.0 V 4.5 RS=VIL 6.0 and MR=VIH IO = 3.2 mA IO = 4.2 mA IO = 20 A IO = 20 A IO = 20 A IO = 4.0 mA IO = 5.2 mA VOL V 2.0 VIH 4.5 or 6.0 VIL 4.5 VIH 6.0 or VIL 6.0 VCC or GND 6.0 VCC or GND VOL V II A ICC quiescent supply current 8.0 80.0 160.0 A IO = 0 December 1990 7 Philips Semiconductors Product specification 14-stage binary ripple counter with oscillator AC CHARACTERISTICS FOR 74HC GND = 0 V; tr = tf = 6 ns; CL = 50 pF Tamb (C) 74HC SYMBOL PARAMETER min. 74HC/HCT4060 TEST CONDITIONS UNIT VCC WAVEFORMS (V) +25 typ. 99 36 29 22 8 6 55 20 16 19 7 6 80 16 14 80 16 14 17 6 5 25 9 7 max. 300 60 51 80 16 14 175 35 30 75 15 13 -40 to +85 min. max. 375 75 64 100 20 17 220 44 37 95 19 16 100 20 17 100 20 17 125 25 21 4.8 24 28 -40 to +125 min. max. 450 90 77 120 24 20 265 53 45 110 22 19 120 24 20 120 24 20 150 30 26 4.0 20 24 tPHL/ tPLH propagation delay RS to Q3 propagation delay Qn to Qn+1 propagation delay MR to Qn output transition time ns 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 Fig.12 tPHL/ tPLH ns Fig.14 tPHL ns Fig.13 tTHL/ tTLH ns Fig.12 tW clock pulse width RS; HIGH or LOW master reset pulse width MR; HIGH removal time MR to RS maximum clock pulse frequency ns Fig.12 tW ns Fig.13 trem 100 28 20 10 17 8 6.0 30 35 26 80 95 ns Fig.13 fmax 2.0 MHz 4.5 6.0 Fig.12 December 1990 8 December 1990 9 Philips Semiconductors DC CHARACTERISTICS FOR 74HCT Output capability: standard (except for RTC and CTC) ICC category: MSI Voltages are referenced to GND (ground = 0 V) Tamb (C) 74HCT SYMBOL PARAMETER min. 14-stage binary ripple counter with oscillator TEST CONDITIONS UNIT +25 typ. max. -40 to +85 -40 to +125 min. max. min. max. VCC (V) 4.5 to 5.5 4.5 to 5.5 4.5 4.5 4.5 4.5 4.5 4.5 4.5 VI OTHER VIH VIL VOH HIGH level input voltage LOW level input voltage HIGH level output voltage RTC output 2.0 0.8 3.98 3.98 4.4 4.4 4.5 4.5 2.0 0.8 3.84 3.84 4.4 4.4 3.84 4.5 4.4 3.84 2.0 0.8 3.7 3.7 4.4 4.4 3.7 4.4 3.7 V V V V V V V V V note 2 note 2 RS=GND and MR=GND RS = VCC and MR = VCC RS=GND and MR=GND RS=VCC and MR=VCC RS = VIH and MR = VIL -IO = 2.6 mA -IO = 0.65 mA -IO = 20 A -IO = 20 A -IO = 3.2 mA -IO = 20 A -IO = 4.0 mA VOH VOH VOH HIGH level output voltage CTC output HIGH level output voltage except RTC output HIGH level output voltage except RTC and CTC outputs LOW level output voltage RTC output LOW level output voltage CTC output LOW level output voltage except RTC output LOW level output voltage except RTC and CTC outputs input leakage current quiescent supply current additional quiescent supply current per input pin for unit load coefficient is 1 (note 1) 3.98 4.4 3.98 VIH or VIL VIH or VIL VOL VOL VOL VOL 0.26 0 0.1 0.26 0 0.1 0.26 0.33 0.1 0.33 0.1 0.33 0.4 0.1 0.4 0.1 0.4 V V V V V 4.5 4.5 4.5 4.5 4.5 RS=VCC and MR=GND RS=VCC and MR=GND RS = VIL and MR = VIH IO = 2.6 mA IO = 20 A IO = 3.2 mA IO = 20 A VIH or VIL VIH or VIL 74HC/HCT4060 IO = 4.0 mA Product specification I ICC ICC 0.1 8.0 100 360 1.0 80.0 450 1.0 490 A A 5.5 5.5 4.5 to 5.5 VCC or GND VCC or GND VCC - 2.1 V 160.0 A IO = 0 other inputs at VCC or GND; IO = 0 Philips Semiconductors Product specification 14-stage binary ripple counter with oscillator Notes 74HC/HCT4060 1. The value of additional quiescent supply current (ICC) for a unit load of 1 is given here. To determine ICC per input, multiply this value by the unit load coefficient shown in the table below. 2. Only input MR (pin 12) has TTL input switching levels for the HCT versions. INPUT MR UNIT LOAD COEFFICIENT 0.40 AC CHARACTERISTICS FOR 74HCT GND = 0 V; tr = tf = 6 ns; CL = 50 pF Tamb (C) 74HCT SYMBOL PARAMETER min. tPHL/ tPLH tPHL/ tPLH tPHL tTHL/ tTLH tW tW trem fmax propagation delay RS to Q3 propagation delay Qn to Qn+1 propagation delay MR to Qn output transition time clock pulse width RS; HIGH or LOW master reset pulse width MR; HIGH removal time MR to RS maximum clock pulse frequency 16 16 26 30 +25 typ. 33 8 21 7 6 6 13 80 max. 66 16 44 15 20 20 33 24 -40 to +85 min. max. 83 20 55 19 24 24 39 20 -40 to +125 min. max. 99 24 66 22 ns ns ns ns ns ns ns MHz 4.5 4.5 4.5 4.5 4.5 4.5 4.5 4.5 Fig.12 Fig.14 Fig.13 Fig.12 Fig.12 Fig.13 Fig.13 Fig.12 UNIT V WAVEFORMS CC (V) TEST CONDITIONS December 1990 10 Philips Semiconductors Product specification 14-stage binary ripple counter with oscillator 74HC/HCT4060 handbook, halfpage g 14 max. 12 MBA333 fs (mA/V) typ. 10 8 6 4 min. Fig.7 Test set-up for measuring forward transconductance gfs = dio / dvi at vo is constant (see also graph Fig.8); MR = LOW. 2 0 1 2 3 4 5 VCC (V) 6 Fig.8 Typical forward transconductance gfs as a function of the supply voltage VCC at Tamb = 25 C. RC OSCILLATOR Fig.9 RC oscillator frequency as a function of Rt and Ct at VCC = 2.0 to 6.0 V; Tamb = 25 C. Ct curve at Rt = 100 k; R2 = 200 k. Rt curve at Ct = 1 nF; R2 = 2 x Rt. Typical formula for oscillator frequency: 1 f osc = ------------------------------2.5 x R t x C t Fig.10 Example of a RC oscillator. TIMING COMPONENT LIMITATIONS The oscillator frequency is mainly determined by RtCt, provided R2 2Rt and R2C2 << RtCt. The function of R2 is to minimize the influence of the forward voltage across the input protection diodes on the frequency. The stray capacitance C2 should be kept as small as possible. In consideration of accuracy, Ct must be larger than the inherent stray capacitance. Rt must be larger than the "ON" resistance in series with it, which typically is 280 at VCC = 2.0 V, 130 at VCC = 4.5 V and 100 at VCC = 6.0 V. The recommended values for these components to maintain agreement with the typical oscillation formula are: Ct > 50 pF, up to any practical value, 10 k < Rt < 1 M. In order to avoid start-up problems, Rt 1 k. December 1990 11 Philips Semiconductors Product specification 14-stage binary ripple counter with oscillator 74HC/HCT4060 TYPICAL CRYSTAL OSCILLATOR In Fig.11, R2 is the power limiting resistor. For starting and maintaining oscillation a minimum transconductance is necessary, so R2 should not be too large. A practical value for R2 is 2.2 k. Fig.11 External components connection for a crystal oscillator. AC WAVEFORMS (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V. (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V. Fig.12 Waveforms showing the clock (RS) to output (Q3) propagation delays, the clock pulse width, the output transition times and the maximum clock frequency. Fig.13 Waveforms showing the master reset (MR) pulse width, the master reset to output (Qn) propagation delays and the master reset to clock (RS) removal time. (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V. Fig.14 Waveforms showing the output (Qn) to Qn+1 propagation delays. PACKAGE OUTLINES See "74HC/HCT/HCU/HCMOS Logic Package Outlines". December 1990 12 This datasheet has been download from: www..com Datasheets for electronics components. |
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